CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware SRAM design and test
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...
Gorde:
| Egile Nagusiak: | , , |
|---|---|
| Formatua: | Livre numérique |
| Hizkuntza: | Anglais |
| Argitaratua: |
Dordrecht :
Springer Netherlands
[20..].
Cham : Springer Nature |
| Edizioa: | 1st ed. 2008. |
| Saila: | Frontiers in Electronic Testing
40 |
| Sarrera elektronikoa: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Oharra: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • CMOS SRAM circuit design and parametric test in nano-scaled technologies, 9781402083624 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9789048178551 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9789048117451 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9781402083624 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9789048178551 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9789048117451 • CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies, Texte imprimé, 9781402083624 |
Aurkibidea:
- and Motivation SRAM Circuit Design and Operation SRAM Cell Stability: Definition, Modeling and Testing Traditional SRAM Fault Models and Test Practices Techniques for Detection of SRAM Cells with Stability Faults Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques