Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phon...
Zapisane w:
| Główni autorzy: | , , |
|---|---|
| Format: | Livre numérique |
| Język: | Anglais |
| Wydane: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Dostęp online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Komentarz: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low power design with high-level power estimation and power-aware synthesis, Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla, New York, Springer, 2012, xxii, 170 p., 978-1-461-40871-0 • Low Power Design with High-Level Power Estimation and Power-Aware Synthesis, Texte imprimé, 9781461408734 • Low Power Design with High-Level Power Estimation and Power-Aware Synthesis, Texte imprimé, 9781489987808 |
| LEADER | 04050nam a22003617a 4500 | ||
|---|---|---|---|
| 001 | 958648 | ||
| 008 | 141128s2012 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN18209118X | ||
| 020 | |a 9781461408727 | ||
| 020 | |a 9781461408727 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Ahuja, Sumit. | |
| 245 | 1 | 0 | |a Low Power Design with High-Level Power Estimation and Power-Aware Synthesis |c by Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla. |
| 260 | |a New York, NY : |b Springer New York. | ||
| 260 | |a Cham : |b Springer Nature, |c 2012. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Introduction -- Related Work -- Background -- Architectural Selection using High Level Synthesis -- Statistical Regression Based Power Models -- Coprocessor Design Space Exploration Using High Level Synthesis -- Regression-based Dynamic Power Estimation for FPGAs -- High Level Simulation Directed RTL Power Estimation -- Applying Verification Collaterals for Accurate Power Estimation -- Power Reduction using High-Level Clock-gating -- Model-Checking to exploit Sequential Clock-gating -- System Level Simulation Guided Approach for Clock-gating -- Conclusions. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives; Covers techniques from RTL/gate-level to hardware software co-design. | ||
| 700 | 1 | |a Lakshminarayana, Avinash. |4 aut | |
| 700 | 1 | |a Shukla, Sandeep Kumar. |4 aut | |
| 776 | 0 | |0 169622967 |t Low power design with high-level power estimation and power-aware synthesis |f Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla |c New York |n Springer |d 2012 |p xxii, 170 p. |z 978-1-461-40871-0 | |
| 776 | 0 | |t Low Power Design with High-Level Power Estimation and Power-Aware Synthesis |b Texte imprimé |z 9781461408734 | |
| 776 | 0 | |t Low Power Design with High-Level Power Estimation and Power-Aware Synthesis |b Texte imprimé |z 9781489987808 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-1-4614-0872-7 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-KNGV8VFR-D |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:74912184X |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/978-1-4614-0872-7 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:752130765 |u https://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/978-1-4614-0872-7 |z Accès INSA CVL | |
| 997 | |0 958648 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||