Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phon...
Sparad:
| Huvudupphovsmän: | , , |
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| Materialtyp: | Livre numérique |
| Språk: | Anglais |
| Publicerad: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Länkar: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Anmärkning: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low power design with high-level power estimation and power-aware synthesis, Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla, New York, Springer, 2012, xxii, 170 p., 978-1-461-40871-0 • Low Power Design with High-Level Power Estimation and Power-Aware Synthesis, Texte imprimé, 9781461408734 • Low Power Design with High-Level Power Estimation and Power-Aware Synthesis, Texte imprimé, 9781489987808 |
| Sammanfattning: | Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives; Covers techniques from RTL/gate-level to hardware software co-design. |
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| Beskrivning: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9781461408727 |
| Tillgång: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |