Nanometer technology designs high-quality delay tests
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip...
Enregistré dans:
| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
New York, NY :
Springer US
2008.
Cham : Springer Nature |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Nanometer Technology Designs, Texte imprimé, 9780387764863 • Perspectives for parallel optical interconnects, Ph. Lalanne, P. Chavel (eds.), Berlin, Springer-Verlag, 1993, 1 volume, ESPRIT basic research series, 3-540-56786-0 • Nanometer Technology Designs, Texte imprimé, 9781441945594 |
Table des matières:
- Introduction to path delay and transition delay fault models and test methods
- At-speed test challenges for nanometer technology designs
- Low-cost tester friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally untestable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering IR-drop effects
- IR-drop tolerant at-speed test pattern generation and application.