Fault-tolerance techniques for SRAM-based FPGAs
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technol...
Guardat en:
| Altres autors: | , , |
|---|---|
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| Col·lecció: | Frontiers in Electronic Testing
32 |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Fault-tolerance techniques for SRAM-based FPGAs, by Fernanda Lima Kastensmidt,... Luigi Carro,... and Ricardo Reis,..., 2006, Dordrecht, Springer, 1 vol. (XV-183 p.), Frontiers in electronic testing, 0-387-31068-1 |
Taula de continguts:
- Radiation Effects in Integrated Circuits Single Event Upset (SEU) Mitigation Techniques Architectural SEU Mitigation Techniques High-Level SEU Mitigation Techniques Triple Modular Redundancy (TMR) Robustness Designing and Testing a TMR Micro-Controller Reducing TMR Overheads: Part I Reducing TMR Overheads: Part II Final Remarks