Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous manufacturing-ready GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of ti...
Uloženo v:
| Hlavní autor: | |
|---|---|
| Médium: | Livre numérique |
| Jazyk: | Anglais |
| Vydáno: |
New York, NY :
Springer New York
2013.
Cham : Springer Nature |
| On-line přístup: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Poznámka: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Design for high performance, low power, and reliable 3D integrated circuits, Sung Kyu Lim, New York, Springer, 2013, 1 vol. (XXVIII-560 p., 978-1-441-99541-4 • Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Texte imprimé, 9781441995438 • Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Texte imprimé, 9781489986962 |
Obsah:
- Regular vs Irregular TSV Placementfor 3D IC
- Steiner Routingfor 3D IC
- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC
- Power Delivery Network Design for 3D IC
- 3D Clock Routing for Pre-bond Testability
- TSV-to-TSV Coupling Analysis and Optimization
- TSV Current Crowding and Power Integrity
- Modeling of Atomic Concentration at the Wire-to-TSV Interface
- Multi-Objective Archetectural Floorplanning for 3D IC
- Thermal-aware Gate-level Placement for 3D IC
- 3D IC Cooling with Micro-Fluidic Channels
- Mechanical Reliability Analysis and Optimization for 3D IC
- Impact of Mechanical Stress on Timing Variation for 3D IC
- Chip/Package Co-Analysis of Mechanical Stress for 3D IC
- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations
- TSV Interfracial Crack Analysis and Optimization
- Ultra High Logic Designs Using Monolithic 3D Integration
- Impact of TSV Scaling on 3D IC Design Quality
- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.