Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous manufacturing-ready GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of ti...
Enregistré dans:
| Hovedforfatter: | |
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| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer New York
2013.
Cham : Springer Nature |
| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Kommentar: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Design for high performance, low power, and reliable 3D integrated circuits, Sung Kyu Lim, New York, Springer, 2013, 1 vol. (XXVIII-560 p., 978-1-441-99541-4 • Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Texte imprimé, 9781441995438 • Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Texte imprimé, 9781489986962 |
| Summary: | This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous manufacturing-ready GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs. Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance. Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements. |
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| Emne beskrivelse: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9781441995421 |
| Adgang: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |