Introduction to Advanced System-on-Chip Test Design and Optimization
SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automat...
Đã lưu trong:
| Tác giả chính: | |
|---|---|
| Định dạng: | Livre numérique |
| Ngôn ngữ: | Anglais |
| Được phát hành: |
New York, NY :
Springer US
[20..].
Cham : Springer Nature |
| Phiên bản: | 1st ed. 2005. |
| Loạt: | Frontiers in Electronic Testing
29 |
| Truy cập trực tuyến: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Chú thích: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Introduction to Advanced System-on-Chip Test Design and Optimization, by Erik Larsson., Boston, MA, Springer US, 2005, Frontiers in Electronic Testing, 978-1-40203-207-3 • Introduction to Advanced System-on-Chip Test Design and Optimization, Texte imprimé, 9781441952691 • Cardiorespiratory and motor coordination, [XXXI International congress of IUPS Helsinki 1989 satellite symposium, Espoo, 15-17 July 1989], ed. H.-P. Koepchen, T. Huopaniemi, Berlin, Springer-Verlag, 1991, xxi, 337 p, 3-540-52279-4 |
Mục lục:
- Testing Concepts Design Flow Design for Test Boundary Scan SOC Design for Testability System Modeling Test Conflicts Test Power Dissipation Test Access Mechanism Test Scheduling SOC Test Applications A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling An Integrated Framework for the Design and Optimization of SOC Test Solutions Efficient Test Solutions for Core-Based Designs Core Selection in the SOC Test Design-Flow Defect-Aware Test Scheduling An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint