Low power hardware synthesis from concurrent action-oriented specifications
Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications Gaurav Singh Sandeep K. Shukla This book introduces novel techniques for generating low-power hardware from a high-level description of a design in terms of Concurrent Action-Oriented Specifications (CAOS). It also describes...
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| Autori principali: | , |
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| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
New York, NY :
Springer New York
2010.
Cham : Springer Nature |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications, Texte imprimé, 9781441964809 • Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications, Texte imprimé, 9781441964823 • Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications, Texte imprimé, 9781489987020 |
| Riassunto: | Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications Gaurav Singh Sandeep K. Shukla This book introduces novel techniques for generating low-power hardware from a high-level description of a design in terms of Concurrent Action-Oriented Specifications (CAOS). It also describes novel techniques for formal verification of such designs. It will provide the readers with definitions of various power optimization and formal verification problems related to CAOS-based synthesis, necessary background concepts, techniques to generate hardware according to the design s power requirements, and detailed experimental results obtained by applying the techniques introduced on realistic hardware designs. Presents detailed analysis of various power optimization problems associated with high-level synthesis, as well as novel techniques for reducing power consumption of hardware designs at a higher level of abstraction; Discusses various formal verification issues associated with synthesizing different possible versions of a hardware design (differing in their latency, area, and/or power consumption); Includes detailed experimental results obtained by applying the techniques introduced on benchmark hardware designs. |
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| Descrizione del documento: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9781441964816 |
| Accesso: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |