SystemVerilog for verification : a guide to learning the testbench language features

SystemVerilog for verification : a guide to learning the testbench language features

New! Expanded! Updated! Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include: The revision of nearly every explanation and code sam...

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Dades bibliogràfiques
Autor principal: Spear, Chris, 1968-
Format: Livre numérique
Idioma:Anglais
Publicat: New York, NY : Springer US 2008.
Cham : Springer Nature
Matèries:
Verilog (langage de description de matériel informatique)
Accés en línia:Accès sur la plateforme de l'éditeur
Accès sur la plateforme Istex
Accès Université d'Orléans
Accès INSA CVL
Nota: Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
Autres localisations: Voir dans le Sudoc
Edition sous un autre format:• SystemVerilog for verification, 9781441945617
• SystemVerilog for verification, 9780387765297
• Economics of wage determination, Heinz König, ed, Berlin, Springer-Verlag, 1990, 1 vol. (X-373 pages), Studies in contemporary economics, 3-540-52324-3
Taula de continguts:
  • 1. Verification Guidelines
  • 1.1 The Verification Process
  • 1.2 The Verification Methodology Manual
  • 1.3 Basic Testbench Functionality
  • 1.4 Directed Testing
  • 1.5 Methodology Basics
  • 1.6 Constrained-Random Stimulus
  • 1.7 What Should You Randomize?
  • 1.8 Functional Coverage
  • 1.9 Testbench Components
  • 1.10 Layered Testbench
  • 1.11 Building a Layered Testbench
  • 1.12 Simulation Environment Phases
  • 1.13 Maximum Code Reuse
  • 1.14 Testbench Performance
  • 1.15 Conclusion
  • 2. Data Types
  • 2.1 Built-in Data Types
  • 2.2 Fixed-Size Arrays
  • 2.3 Dynamic Arrays
  • 2.4 Queues
  • 2.5 Associative Arrays
  • 2.6 Linked Lists
  • 2.7 Array Methods
  • 2.8 Choosing a Storage Type
  • 2.9 Creating New Types with typedef
  • 2.10 Creating User-Defined Structures
  • 2.11 Type conversion
  • 2.12 Enumerated Types
  • 2.13 Constants
  • 2.14 Strings
  • 2.15 Expression Width
  • 2.16 Conclusion
  • 3. Procedural Statements and Routines
  • 3.1 Procedural Statements
  • 3.2 Tasks, Functions, and Void Functions
  • 3.3 Task and Function Overview
  • 3.4 Routine Arguments
  • 3.5 Returning from a Routine
  • 3.6 Local Data Storage
  • 3.7 Time Values
  • 3.8 Conclusion
  • 4. Connecting The Testbench and Design
  • 4.1 Separating the Testbench and Design
  • 4.2 The Interface Construct
  • 4.3 Stimulus Timing
  • 4.4 Interface Driving and Sampling
  • 4.5 Connecting It All Together
  • 4.6 Top-Level Scope
  • 4.7 Program - Module Interactions
  • 4.8 SystemVerilog Assertions

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