Defect-oriented testing for nano-metric CMOS VLSI circuits : 2nd edition
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptabl...
Enregistré dans:
| Auteur principal: | |
|---|---|
| Autres auteurs: | |
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| Collection: | Frontiers in electronic testing
34 |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits, Texte imprimé, 9780387465463 |
Table des matières:
- Functional and Parametric Defect Models Digital CMOS Fault Modeling Defects in Logic Circuits and their Test Implications Testing Defects and Parametric Variations in RAMs Defect-Oriented Analog Testing Yield Engineering Conclusion