Design for manufacturability and yield for nano-scale CMOS
As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect...
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| Auteurs principaux: | , |
|---|---|
| Formato: | Livre numérique |
| Idioma: | Anglais |
| Publicado em: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| Colecção: | Series on Integrated Circuits and Systems
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| Acesso em linha: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Design for Manufacturability and Yield for Nano-Scale CMOS, Texte imprimé, 9789048173037 • Design for Manufacturability and Yield for Nano-Scale CMOS, Texte imprimé, 9789048110216 • Design for Manufacturability and Yield for Nano-Scale CMOS, Texte imprimé, 9781402051876 |
Sumário:
- Random Defects
- Systematic Yield - Lithography
- Systematic Yield - Chemical Mechanical Polishing (CMP)
- Variability & Parametric Yield
- Design for Yield
- Yield Prediction
- Conclusions.