Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction te...
Enregistré dans:
| Auteur principal: | |
|---|---|
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| Collection: | Springer Series in Advanced Microelectronics
25 |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048109807 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048172788 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9781402050800 |
Table des matières:
- TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN
- LOGIC WITH MULTIPLE SUPPLY VOLTAGES
- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES
- FORCING OF TRANSISTOR STACKS
- POWER GATING
- CONCLUSION.