Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction te...
Enregistré dans:
| Auteur principal: | |
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| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| Collection: | Springer Series in Advanced Microelectronics
25 |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048109807 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048172788 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9781402050800 |
| Résumé: | In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side. |
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| Description: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9781402050817 |
| ISSN: | 2197-6643 |
| Accès: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |