Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction te...
Na minha lista:
| Autor principal: | |
|---|---|
| Formato: | Livre numérique |
| Idioma: | Anglais |
| Publicado em: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| coleção: | Springer Series in Advanced Microelectronics
25 |
| Acesso em linha: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048109807 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9789048172788 • Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, Texte imprimé, 9781402050800 |
| LEADER | 03675nam a22003497a 4500 | ||
|---|---|---|---|
| 001 | 938175 | ||
| 008 | 080410s2007 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN123116554 | ||
| 020 | |a 9781402050817 | ||
| 020 | |a 9781402050817 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Henzler, Stephan. | |
| 245 | 1 | 0 | |a Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies |c by Stephan Henzler. |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2007. | ||
| 490 | 0 | |a Springer Series in Advanced Microelectronics |v 25 |x 2197-6643 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN -- LOGIC WITH MULTIPLE SUPPLY VOLTAGES -- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES -- FORCING OF TRANSISTOR STACKS -- POWER GATING -- CONCLUSION. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side. | ||
| 776 | 0 | |t Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies |b Texte imprimé |z 9789048109807 | |
| 776 | 0 | |t Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies |b Texte imprimé |z 9789048172788 | |
| 776 | 0 | |t Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies |b Texte imprimé |z 9781402050800 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/1-4020-5081-X |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-QGBN9V7C-2 |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:747902399 |u https://ezproxy.univ-orleans.fr/login?url=https://dx.doi.org/10.1007/1-4020-5081-X |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:75091548X |u https://ezproxy.insa-cvl.fr/login?qurl=https://dx.doi.org/10.1007/1-4020-5081-X |z Accès INSA CVL | |
| 997 | |0 938175 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||