Leakage in Nanometer CMOS Technologies
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...
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| Format: | Livre numérique |
| Sprache: | Anglais |
| Veröffentlicht: |
New York, NY :
Springer US
[20..].
Cham : Springer Nature |
| Ausgabe: | 1st ed. 2006. |
| Schriftenreihe: | Integrated Circuits and Systems
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| Online Zugang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
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Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Leakage in nanometer CMOS technologies, [edited by] Siva G. Narendra, Anantha Chandrakasan, 1st ed., New York, NY, Springer, 2005, X-307 p., Series on integrated circuits and systems, 0-387-25737-3 • Leakage in Nanometer CMOS Technologies, Texte imprimé, 9781441938268 • Leakage in Nanometer CMOS Technologies, Texte imprime, 9780387506838 |
Inhaltsangabe:
- Taxonomy of Leakage: Sources, Impact, and Solutions Leakage Dependence on Input Vector Power Gating and Dynamic Voltage Scaling Methodologies for Power Gating Body Biasing Process Variation and Adaptive Design Memory Leakage Reduction Active Leakage Reduction and Multi-Performance Devices Impact of Leakage Power and Variation on Testing Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors Case Study: Leakage Reduction in the Intel Xscale Microprocessor Transistor Design to Reduce Leakage