Leakage in Nanometer CMOS Technologies
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...
Kaydedildi:
| Yazar: | |
|---|---|
| Diğer Yazarlar: | |
| Materyal Türü: | Livre numérique |
| Dil: | Anglais |
| Baskı/Yayın Bilgisi: |
New York, NY :
Springer US
[20..].
Cham : Springer Nature |
| Edisyon: | 1st ed. 2006. |
| Seri Bilgileri: | Integrated Circuits and Systems
|
| Online Erişim: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Not: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Leakage in nanometer CMOS technologies, [edited by] Siva G. Narendra, Anantha Chandrakasan, 1st ed., New York, NY, Springer, 2005, X-307 p., Series on integrated circuits and systems, 0-387-25737-3 • Leakage in Nanometer CMOS Technologies, Texte imprimé, 9781441938268 • Leakage in Nanometer CMOS Technologies, Texte imprime, 9780387506838 |
| LEADER | 03982nam a22003617a 4500 | ||
|---|---|---|---|
| 001 | 1403659 | ||
| 008 | 080410q2000 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN123106931 | ||
| 020 | |a 9780387281339 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Narendra, Siva G. | |
| 245 | 1 | 0 | |a Leakage in Nanometer CMOS Technologies |c by Siva G. Narendra, Anantha Chandrakasan. |
| 250 | |a 1st ed. 2006. | ||
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c [20..]. | ||
| 490 | 0 | |a Integrated Circuits and Systems |x 1558-9420 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 1 | |a Taxonomy of Leakage: Sources, Impact, and Solutions Leakage Dependence on Input Vector Power Gating and Dynamic Voltage Scaling Methodologies for Power Gating Body Biasing Process Variation and Adaptive Design Memory Leakage Reduction Active Leakage Reduction and Multi-Performance Devices Impact of Leakage Power and Variation on Testing Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors Case Study: Leakage Reduction in the Intel Xscale Microprocessor Transistor Design to Reduce Leakage | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers | ||
| 700 | 1 | |a Chandrakasan, Anantha P., |d 19..- |4 pbd | |
| 776 | 0 | |0 094683808 |t Leakage in nanometer CMOS technologies |f [edited by] Siva G. Narendra, Anantha Chandrakasan |e 1st ed. |c New York, NY |n Springer |d 2005 |p X-307 p. |s Series on integrated circuits and systems |z 0-387-25737-3 | |
| 776 | 0 | |t Leakage in Nanometer CMOS Technologies |b Texte imprimé |z 9781441938268 | |
| 776 | 0 | |t Leakage in Nanometer CMOS Technologies |b Texte imprime |z 9780387506838 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/0-387-28133-9 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-1L3FQ29Q-1 |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:876782659 |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/0-387-28133-9 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:876785984 |u uhttps://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/0-387-28133-9 |z Accès INSA CVL | |
| 997 | |0 1403659 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||