VLSI Physical Design: From Graph Partitioning to Timing Closure
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which i...
Tallennettuna:
| Päätekijät: | , , , |
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| Aineistotyyppi: | Livre numérique |
| Kieli: | Anglais |
| Julkaistu: |
Dordrecht :
Springer Netherlands
2011.
Cham : Springer Nature |
| Linkit: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Huomautus: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • VLSI Physical Design: From Graph Partitioning to Timing Closure, Texte imprimé, 9789048195909 • VLSI Physical Design: From Graph Partitioning to Timing Closure, Texte imprimé, 9789048195923 • VLSI Physical Design: From Graph Partitioning to Timing Closure, Texte imprimé, 9789400790209 |
| Yhteenveto: | Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design,wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure. For Slides and Other Information: https://www.ifte.de/books/eda/index.html. |
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| Huomautukset: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9789048195916 |
| Pääsy: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |