Low-power variation-tolerant design in nanometer silicon :: SCD d'Orléans

Low-power variation-tolerant design in nanometer silicon

Low-power variation-tolerant design in nanometer silicon

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-thresh...

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Dettagli Bibliografici
Altri autori:	Bhunia, Swarup (Direttore editoriale), Mukhopadhyay, Saibal (Direttore editoriale)
Natura:	Livre numérique
Lingua:	Anglais
Pubblicazione:	New York, NY : Springer US 2011. Cham : Springer Nature
Accesso online:	Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL
Nota:	Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale)
Autres localisations:	Voir dans le Sudoc
Edition sous un autre format:	• Low-power variation-tolerant design in nanometer silicon, Swarup Bhunia, Saibal Mukhopadhyay, editors, New York, Springer, 2011, 1 vol. (XV-440 p.), 978-1-441-97417-4 • Low-Power Variation-Tolerant Design in Nanometer Silicon, Texte imprimé, 9781441974198 • Low-Power Variation-Tolerant Design in Nanometer Silicon, Texte imprimé, 9781489981578

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