Application-Specific Mesh-based Heterogeneous FPGA Architectures
Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However,...
সংরক্ষণ করুন:
| প্রধান লেখক: | , |
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| বিন্যাস: | Livre numérique |
| ভাষা: | Anglais |
| প্রকাশিত: |
New York, NY :
Springer New York
2011.
Cham : Springer Nature |
| অনলাইন ব্যবহার করুন: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| টীকা: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Application-Specific Mesh-based Heterogeneous FPGA architectures, Husain Parvez, Habib Mehrez, 2011, New York, Springer, 1 vol. (XVII-150 p.), 978-1-4419-7927-8 • Application-Specific Mesh-based Heterogeneous FPGA Architectures, Texte imprimé, 9781441979292 • Application-Specific Mesh-based Heterogeneous FPGA Architectures, Texte imprimé, 9781489987884 |
| সংক্ষিপ্ত: | Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance. |
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| উপাদানের বিবরণ: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| আইসবিএন: | 9781441979285 |
| প্রবেশাধিকার: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |