The Power of Assertions in SystemVerilog
The Power of Assertions in SystemVerilog is a comprehensive book that enables the reader to reap the full benefits of assertion-based verification in the quest to abate hardware verification cost. The book is divided into three parts. The first part introduces assertions, SystemVerilog and its simul...
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| 主要な著者: | , , , |
|---|---|
| フォーマット: | Livre numérique |
| 言語: | Anglais |
| 出版事項: |
New York, NY :
Springer US
2010.
Cham : Springer Nature |
| オンライン･アクセス: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| 注記: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • The Power of Assertions in SystemVerilog, Texte imprimé, 9781441965998 • The Power of Assertions in SystemVerilog, Texte imprimé, 9781441966018 |
| LEADER | 04236nam a22003617a 4500 | ||
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| 001 | 967896 | ||
| 008 | 110106s2010 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN149033664 | ||
| 020 | |a 9781441966001 | ||
| 020 | |a 9781441966001 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Cerny, Eduard. | |
| 245 | 1 | 0 | |a The Power of Assertions in SystemVerilog |c by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2010. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Opening -- SystemVerilog Language and Simulation Semantics Overview -- Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Let Sequence and Property Declarations Inference -- Advanced Properties -- Advanced Sequences -- to Assertion Based Formal Verification -- Formal Verification and Models -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Formal Semantics -- Checkers and Assertion Libraries -- Checkers -- Checkers in Formal Verification -- Checker Libraries -- Future Enhancements. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a The Power of Assertions in SystemVerilog is a comprehensive book that enables the reader to reap the full benefits of assertion-based verification in the quest to abate hardware verification cost. The book is divided into three parts. The first part introduces assertions, SystemVerilog and its simulation semantics. The second part delves into the details of assertions and their semantics. All property operators, in conjunction with ease-of-use features and examples, are discussed to illustrate the immense expressive power of the language. The third part presents an extended description of checkers and a methodology for building reusable checker libraries. The book concludes by outlining some desirable future enhancements. Detailed descriptions of the language features are provided throughout the book, along with their uses and how they play together to construct powerful sets of property checkers. The exposition of the features is supplemented with examples that take the reader step-by-step, from intuitive comprehension to much greater depth of understanding, enabling the reader to become an expert user. A unique aspect of the book is that it is oriented toward both simulation and formal verification. The semantics is discussed in terms of both simulation events and formal definition. This blended approach imparts profound conceptual and practical guidance for a broader spectrum of readers. The Power of Assertions in SystemVerilog is a valuable reference for design engineers, verification engineers, tool builders and educators. | ||
| 700 | 1 | |a Dudani, Surrendra. |4 aut | |
| 700 | 1 | |a Havlicek, John. |4 aut | |
| 700 | 1 | |a Korchemny, Dmitry. |4 aut | |
| 776 | 0 | |t The Power of Assertions in SystemVerilog |b Texte imprimé |z 9781441965998 | |
| 776 | 0 | |t The Power of Assertions in SystemVerilog |b Texte imprimé |z 9781441966018 | |
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