Scalable Multi-core Architectures : Design Methodologies and Tools
As Moore s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures....
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| Autore principale: | |
|---|---|
| Altri autori: | , |
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Scalable Multi-core Architectures, Texte imprimé, 9781441967770 • Scalable Multi-core Architectures, Texte imprimé, 9781441967794 • Scalable Multi-core Architectures, Texte imprimé, 9781489993151 |
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| 100 | 1 | |a Soudris, Dimitrios, |d 1964- | |
| 245 | 1 | 0 | |a Scalable Multi-core Architectures : |b Design Methodologies and Tools |c edited by Dimitrios Soudris, Axel Jantsch. |
| 260 | |a New York, NY : |b Springer New York. | ||
| 260 | |a Cham : |b Springer Nature, |c 2012. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Part I: HS/SW/ Building Blocks: Architecture, Methods, and Techniques -- 1. Memory Architecture and Management in an NoC Platform -- 2. Application-Specific Multi-Threaded Dynamic Memory Management -- 3. Power Management Architecture in McNoC -- 4. ASIP Exploration and Design -- Part II: System-level Exploration -- 5. System Exploration -- 6. MPA: Parallelization Made Easy -- Part III: Industrial Applications -- 7. MPSoC Architecture Performance Analysis for Agile SDR Radio Applications -- 8. Application of the MOSART Flow on the WiMAX (802.16e) PHY. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a As Moore s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures. This book provides a current snapshot of industrial and academic research, conducted as part of the European FP7 MOSART project, addressing urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies. Describes trends towards distributed memory architectures and distributed power management; Integrates Network on Chip with distributed, shared memory architectures; Demonstrates novel design methodologies and frameworks for multi-core design space exploration; Shows how midlleware services (dynamic data management) can be integrated into and support by the platform. . | ||
| 700 | 1 | |a Soudris, Dimitrios. |4 pbd | |
| 700 | 1 | |a Jantsch, Axel. |4 pbd | |
| 776 | 0 | |t Scalable Multi-core Architectures |b Texte imprimé |z 9781441967770 | |
| 776 | 0 | |t Scalable Multi-core Architectures |b Texte imprimé |z 9781441967794 | |
| 776 | 0 | |t Scalable Multi-core Architectures |b Texte imprimé |z 9781489993151 | |
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