Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs
Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design o...
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| Hauptverfasser: | , , |
|---|---|
| Format: | Livre numérique |
| Sprache: | Anglais |
| Veröffentlicht: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Online Zugang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Anmerkung: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Texte imprimé, 9781461407874 • Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Texte imprimé, 9781461407898 • Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Texte imprimé, 9781489987877 |
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| 008 | 130325s2012 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN168294893 | ||
| 020 | |a 9781461407881 | ||
| 020 | |a 9781461407881 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Shen, Ruijing. | |
| 245 | 1 | 0 | |a Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs |c by Ruijing Shen, Sheldon X.-D. Tan, Hao Yu. |
| 260 | |a New York, NY : |b Springer New York. | ||
| 260 | |a Cham : |b Springer Nature, |c 2012. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Fundamentals of Statistical Analysis -- Statistical Full-Chip Leakage Power Analysis -- Statistical Full-Chip Dynamic Power Analysis -- Statistical Parasitic Extraction -- Statistical Compact Modeling and Reduction of Interconnects -- Statistical Analysis of Global Interconnects -- Statistical Analysis and Modeling for Analog and Mixed-Signal Circuits. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithmwith practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. . | ||
| 700 | 1 | |a Tan, Sheldon X.-D. |4 aut | |
| 700 | 1 | |a Yu, Hao. |4 aut | |
| 776 | 0 | |t Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs |b Texte imprimé |z 9781461407874 | |
| 776 | 0 | |t Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs |b Texte imprimé |z 9781461407898 | |
| 776 | 0 | |t Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs |b Texte imprimé |z 9781489987877 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-1-4614-0788-1 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-Q9MJ6S0M-M |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:749603887 |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/978-1-4614-0788-1 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:752352253 |u https://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/978-1-4614-0788-1 |z Accès INSA CVL | |
| 997 | |0 957891 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||