Direct transistor-level layout for digital blocks
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...
সংরক্ষণ করুন:
| প্রধান লেখক: | , |
|---|---|
| বিন্যাস: | Livre numérique |
| ভাষা: | Anglais |
| প্রকাশিত: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| বিষয়গুলি: | |
| অনলাইন ব্যবহার করুন: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| টীকা: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Direct Transistor-Level Layout for Digital Blocks, Texte imprimé, 9780387522272 • Direct Transistor-Level Layout for Digital Blocks, Texte imprimé, 9781475779516 • Direct transistor-level layout for digital blocks, Prakash Gopalakrishnan, Rob A. Rutenbar, Boston, Kluwer Academic Publishers, 2004, VII-125 p., 1-402-07665-7 |
সূচিপত্রের সারণি:
- Circuit Structure and Clustering Global Placement Detailed Placement and Layout Results Timing-Driven Placement Conclusion.