Direct transistor-level layout for digital blocks
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...
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| Auteurs principaux: | , |
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| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
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Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Direct Transistor-Level Layout for Digital Blocks, Texte imprimé, 9780387522272 • Direct Transistor-Level Layout for Digital Blocks, Texte imprimé, 9781475779516 • Direct transistor-level layout for digital blocks, Prakash Gopalakrishnan, Rob A. Rutenbar, Boston, Kluwer Academic Publishers, 2004, VII-125 p., 1-402-07665-7 |
| Summary: | Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers. |
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| Emne beskrivelse: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9781402080630 |
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