Functional verification of programmable embedded architectures : A top-down approach
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
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| Principais autores: | , |
|---|---|
| Formato: | Livre numérique |
| Idioma: | Anglais |
| Publicado em: |
New York, NY :
Springer US
2005.
Cham : Springer Nature |
| Acesso em linha: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387507767 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9781489973368 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387261430 |
Sumário:
- to Functional Verification
- Architecture Specification
- Architecture Specification
- Validation of Specification
- Top-Down Validation
- Executable Model Generation
- Design Validation
- Functional Test Generation
- Future Directions
- Conclusions.