Functional verification of programmable embedded architectures : A top-down approach
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
Tallennettuna:
| Päätekijät: | , |
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| Aineistotyyppi: | Livre numérique |
| Kieli: | Anglais |
| Julkaistu: |
New York, NY :
Springer US
2005.
Cham : Springer Nature |
| Linkit: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Huomautus: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387507767 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9781489973368 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387261430 |
| Yhteenveto: | Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems. |
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| Huomautukset: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9780387263991 |
| Pääsy: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |