Functional verification of programmable embedded architectures : A top-down approach
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
保存先:
| 主要な著者: | , |
|---|---|
| フォーマット: | Livre numérique |
| 言語: | Anglais |
| 出版事項: |
New York, NY :
Springer US
2005.
Cham : Springer Nature |
| オンライン･アクセス: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| 注記: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387507767 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9781489973368 • Functional Verification of Programmable Embedded Architectures, Texte imprimé, 9780387261430 |
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| 100 | 1 | |a Mishra, Prabhat, |d 1973- | |
| 245 | 1 | 0 | |a Functional verification of programmable embedded architectures : |b A top-down approach |c by Prabhat Mishra, Nikil D. Dutt. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2005. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a to Functional Verification -- Architecture Specification -- Architecture Specification -- Validation of Specification -- Top-Down Validation -- Executable Model Generation -- Design Validation -- Functional Test Generation -- Future Directions -- Conclusions. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems. | ||
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| 776 | 0 | |t Functional Verification of Programmable Embedded Architectures |b Texte imprimé |z 9780387507767 | |
| 776 | 0 | |t Functional Verification of Programmable Embedded Architectures |b Texte imprimé |z 9781489973368 | |
| 776 | 0 | |t Functional Verification of Programmable Embedded Architectures |b Texte imprimé |z 9780387261430 | |
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