Reconfigurable Computing : Accelerating Computation with Field-Programmable Gate Arrays
placedintohardware. Thismethodologyismoste?ectivewhentheapplication shows 90/10 behavior 90% of execution time in 10% of the code. By placing such compute intensive blocks in hardware, the NAPA could achieve 1 2 orders of magnitude performance improvement over DSP processors. TBT System ToggleBus Po...
Tallennettuna:
| Päätekijät: | , |
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| Aineistotyyppi: | Livre numérique |
| Kieli: | Anglais |
| Julkaistu: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| Linkit: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Huomautus: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Reconfigurable computing, accelerating computation with field-programmable gate arrays, Maya B. Gokhale, 1. Ed., Berlin, Springer US, 2005, (1 vol.) X-238 p., 0-387-26105-2 |
| Yhteenveto: | placedintohardware. Thismethodologyismoste?ectivewhentheapplication shows 90/10 behavior 90% of execution time in 10% of the code. By placing such compute intensive blocks in hardware, the NAPA could achieve 1 2 orders of magnitude performance improvement over DSP processors. TBT System ToggleBus Port Tranceiver ALP CR32 RPC Compact RISC Reconfigurable 32 Bit Processor Pipeline Cntlr Adaptive Logic CIO Processor External XMC Configurable Extended Memory I/O Controller PMA Memory Pipeline Interface Memory Array CR32 SMA Scratchpad Peripheral Memory Array Devices Fig. 3. 14. NAPA 1000 Following these research proposals, commercial FPGA vendors began - fering embedded processors in their FPGA product lines. The Triscend chip was one of the ?rst such products, with an 8-bit microcontroller. More - cently, Altera produced the Excalibur chip with an embedded ARM, and Xilinx followed with embedded PowerPC processors. Stretch, Inc. proposes a OneChip-like architecture in which the con?gurable logic shares register ?les with a Tensilica processor. 3. 3 Summary Recon?gurable logic has found its way into virtually every part of the parallel processing hierarchy. Millions of system gates are available for Instructi- level parallelism within the recon?gurable fabric. By sharing registers or - ternal busses with a conventional microprocessor, co-processor performance is even more accelerated through low latency, high bandwidth communication 50 3 Recon?gurable Computing Systems between processor and recon?gurable logic. In the I/O model, an FPGA - ray can process large granularity compute- and/or data-intensive tasks for the processor |
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| Huomautukset: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9780387261065 |
| Pääsy: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |