Constraining Designs for Synthesis and Timing Analysis : A Practical Guide to Synopsys Design Constraints (SDC)
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis...
محفوظ في:
| المؤلفون الرئيسيون: | , |
|---|---|
| التنسيق: | Livre numérique |
| اللغة: | Anglais |
| منشور في: |
New York, NY :
Springer New York
2013.
Cham : Springer Nature |
| الوصول للمادة أونلاين: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| ملاحظة: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781461432685 • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781461432708 • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781489989161 |
جدول المحتويات:
- Introduction
- Synthesis Basics
- Timing Analysis and Constraints
- SDC Extensions through Tcl
- Clocks
- Generated Clocks
- Clock Groups
- Other Clock Characteristics
- Port Delays
- Completing Port Constraints
- False Paths
- Multi Cycle Paths
- Combinatorial Paths
- Modal Analysis
- Managing Your Constraints
- Miscellaneous SDC Commands
- XDC: Xilinx Extensions To SDC.