Constraining Designs for Synthesis and Timing Analysis : A Practical Guide to Synopsys Design Constraints (SDC)
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis...
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| Autori principali: | , |
|---|---|
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
New York, NY :
Springer New York
2013.
Cham : Springer Nature |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781461432685 • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781461432708 • Constraining Designs for Synthesis and Timing Analysis, Texte imprimé, 9781489989161 |
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| 008 | 130704s2013 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN170487369 | ||
| 020 | |a 9781461432692 | ||
| 020 | |a 9781461432692 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Gangadharan, Sridhar. | |
| 245 | 1 | 0 | |a Constraining Designs for Synthesis and Timing Analysis : |b A Practical Guide to Synopsys Design Constraints (SDC) |c by Sridhar Gangadharan, Sanjay Churiwala. |
| 260 | |a New York, NY : |b Springer New York. | ||
| 260 | |a Cham : |b Springer Nature, |c 2013. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. · Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; · Includes key topics of interest to a synthesis, static timing analysis or place and route engineer; · Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; · Explains fundamental concepts and provides exact command syntax. | ||
| 700 | 1 | |a Churiwala, Sanjay. |4 aut | |
| 776 | 0 | |t Constraining Designs for Synthesis and Timing Analysis |b Texte imprimé |z 9781461432685 | |
| 776 | 0 | |t Constraining Designs for Synthesis and Timing Analysis |b Texte imprimé |z 9781461432708 | |
| 776 | 0 | |t Constraining Designs for Synthesis and Timing Analysis |b Texte imprimé |z 9781489989161 | |
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