Electromigration modeling at circuit layout level
Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has...
Enregistré dans:
| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
Singapore :
Springer Nature Singapore
[20..].
Cham : Springer Nature |
| Édition: | 1st ed. 2013. |
| Collection: | SpringerBriefs in Reliability
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| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Electromigration Modeling at Circuit Layout Level, Texte imprimé, 9789814451222 • Electromigration modeling at circuit layout level, Cher Ming Tan, Feifei He, Singapore, Springer, 2013, 1 vol. (x-103 p.), SpringerBriefs in applied sciences and technology, 978-981-445120-8 |
Table des matières:
- Introduction 3D Circuit Model Construction and Simulation Comparison of EM Performance in Circuit Structure and Test Structure Interconnect EM Reliability Modeling at Circuit Layout Level Conclusion