Electromigration modeling at circuit layout level

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels.  Electromigration (EM) of interconnects has...

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Autors principals: Tan, Cher Ming, 1959-, He, Feifei (Autor)
Format: Livre numérique
Idioma:Anglais
Publicat: Singapore : Springer Nature Singapore [20..].
Cham : Springer Nature
Edició:1st ed. 2013.
Col·lecció:SpringerBriefs in Reliability
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Edition sous un autre format:• Electromigration Modeling at Circuit Layout Level, Texte imprimé, 9789814451222
• Electromigration modeling at circuit layout level, Cher Ming Tan, Feifei He, Singapore, Springer, 2013, 1 vol. (x-103 p.), SpringerBriefs in applied sciences and technology, 978-981-445120-8
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Sumari:Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels.  Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level. 
Descripció de l’ítem:Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
ISBN:9789814451215
ISSN:2196-1131
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