Variation-aware adaptive voltage scaling for sigital CMOS circuits
Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperat...
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| Autore principale: | |
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| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
Dordrecht :
Springer Netherlands
2013.
Cham : Springer Nature |
| Serie: | Springer Series in Advanced Microelectronics
41 |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, Texte imprimé, 9789400761957 • Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, Texte imprimé, 9789400761971 • Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, Texte imprimé, 9789401783675 |
| Riassunto: | Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted on the fly by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits. |
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| Descrizione del documento: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9789400761964 |
| ISSN: | 2197-6643 |
| Accesso: | Accès en ligne pour les établissements français bénéficiaires des licences nationales Accès soumis à abonnement pour tout autre établissement Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 |