Wafer level 3-D ICs process technology
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for impro...
Salvato in:
| Altri autori: | , , |
|---|---|
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| Edizione: | 1st ed. 2008. |
| Serie: | Integrated Circuits and Systems
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| Soggetti: | |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
L'impression du document génère 300 p. Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Wafer Level 3-D ICs Process Technology, Texte imprimé, 9780387765327 |
Sommario:
- Overview of Wafer-Level 3D ICs Monolithic 3D Integrated Circuits Stacked CMOS Technologies Wafer-Bonding Technologies and Strategies for 3D ICs Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies Cu Wafer Bonding for 3D IC Applications Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding An SOI-Based 3D Circuit Integration Technology 3D Fabrication Options for High-Performance CMOS Technology 3D Integration Based upon Dielectric Adhesive Bonding Direct Hybrid Bonding 3D Memory Circuit Architectures for 3D Integration Thermal Challenges of 3D ICs Status and Outlook