Wafer level 3-D ICs process technology

Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for impro...

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Detalhes bibliográficos
Outros Autores: Gutmann, Ronald J. (Editor), Reif, L. Rafael (Editor), Tan, Chuan Seng (Editor)
Formato: Livre numérique
Idioma:Anglais
Publicado em: New York, NY : Springer US : Imprint: Springer [20..].
Cham : Springer Nature
Edição:1st ed. 2008.
coleção:Integrated Circuits and Systems
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Edition sous un autre format:• Wafer Level 3-D ICs Process Technology, Texte imprimé, 9780387765327
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245 1 0 |a Wafer level 3-D ICs process technology   |c Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif, editors. 
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505 1 |a Overview of Wafer-Level 3D ICs Monolithic 3D Integrated Circuits Stacked CMOS Technologies Wafer-Bonding Technologies and Strategies for 3D ICs Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies Cu Wafer Bonding for 3D IC Applications Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding An SOI-Based 3D Circuit Integration Technology 3D Fabrication Options for High-Performance CMOS Technology 3D Integration Based upon Dielectric Adhesive Bonding Direct Hybrid Bonding 3D Memory Circuit Architectures for 3D Integration Thermal Challenges of 3D ICs Status and Outlook 
506 |a Accès en ligne pour les établissements français bénéficiaires des licences nationales 
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520 |a Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration. Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration 
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