The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits : The semi-empirical and compact model approaches
How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The r...
Tallennettuna:
| Päätekijä: | |
|---|---|
| Aineistotyyppi: | Livre numérique |
| Kieli: | Anglais |
| Julkaistu: |
New York, NY :
Springer US
2010.
Cham : Springer Nature |
| Sarja: | Analog Circuits and Signal Processing
|
| Linkit: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Huomautus: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits, the semi-empirical and compact model approaches, by Paul G.A. Jespers,..., Dordrecht, Springer, 2010, 1 volume (XVI-171 p.), Analog circuits and signal processing, 978-0-387-47100-6 • The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, Texte imprimé, 9780387564388 • The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, Texte imprimé, 9781461425052 |
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| 100 | 1 | |a Jespers, Paul G.A. | |
| 245 | 1 | 0 | |a The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits : |b The semi-empirical and compact model approaches |c by Paul Jespers. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2010. | ||
| 490 | 0 | |a Analog Circuits and Signal Processing |x 2197-1854 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests. | ||
| 776 | 0 | |0 146977734 |t The gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits |o the semi-empirical and compact model approaches |f by Paul G.A. Jespers,... |c Dordrecht |n Springer |d 2010 |p 1 volume (XVI-171 p.) |s Analog circuits and signal processing |z 978-0-387-47100-6 | |
| 776 | 0 | |t The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits |b Texte imprimé |z 9780387564388 | |
| 776 | 0 | |t The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits |b Texte imprimé |z 9781461425052 | |
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