On and off-chip Crosstalk avoidance in VLSI Design
On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus t...
में बचाया:
| मुख्य लेखकों: | , , |
|---|---|
| स्वरूप: | Livre numérique |
| भाषा: | Anglais |
| प्रकाशित: |
New York, NY :
Springer US
2010.
Cham : Springer Nature |
| ऑनलाइन पहुंच: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| टिप्पणी: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • On and Off-Chip Crosstalk Avoidance in VLSI Design, Texte imprimé, 9781441909466 • On and Off-Chip Crosstalk Avoidance in VLSI Design, Texte imprimé, 9781441909480 • On and Off-Chip Crosstalk Avoidance in VLSI Design, Texte imprimé, 9781489983275 |
| LEADER | 04500nam a22003617a 4500 | ||
|---|---|---|---|
| 001 | 943233 | ||
| 008 | 110106s2010 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN149075316 | ||
| 020 | |a 9781441909473 | ||
| 020 | |a 9781441909473 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Duan, Chunjie. | |
| 245 | 1 | 0 | |a On and off-chip Crosstalk avoidance in VLSI Design |c by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2010. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford. | ||
| 700 | 1 | |a LaMeres, Brock J., |d 19..- |4 aut | |
| 700 | 1 | |a Khatri, Sunil P. |4 aut | |
| 776 | 0 | |t On and Off-Chip Crosstalk Avoidance in VLSI Design |b Texte imprimé |z 9781441909466 | |
| 776 | 0 | |t On and Off-Chip Crosstalk Avoidance in VLSI Design |b Texte imprimé |z 9781441909480 | |
| 776 | 0 | |t On and Off-Chip Crosstalk Avoidance in VLSI Design |b Texte imprimé |z 9781489983275 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-1-4419-0947-3 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-VRGXVPH5-R |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:747827532 |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/978-1-4419-0947-3 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:750844760 |u https://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/978-1-4419-0947-3 |z Accès INSA CVL | |
| 997 | |0 943233 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||