Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
Uloženo v:
| Hlavní autor: | |
|---|---|
| Médium: | Livre numérique |
| Jazyk: | Anglais |
| Vydáno: |
Dordrecht :
Springer Netherlands
[20..].
Cham : Springer Nature |
| Vydání: | 1st ed. 2009. |
| Edice: | Lecture Notes in Electrical Engineering
34 |
| Témata: | |
| On-line přístup: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Poznámka: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Designing Reliable and Efficient Networks on Chips, Texte imprimé, 9781402097560 |
Obsah:
- NoC Design Methods Designing Crossbar Based Systems Netchip Tool Flow for NoC Design Designing Standard Topologies Designing Custom Topologies Supporting Multiple Applications Supporting Dynamic Application Patterns NoC Reliability Mechanisms Timing-Error Tolerant NoC Design Analysis of NoC Error Recovery Schemes Fault-Tolerant Route Generation NoC Support for Reliable On-Chip Memories Conclusions and Future Directions