Designing Reliable and Efficient Networks on Chips

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...

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書誌詳細
第一著者: Murali, Srinivasan
フォーマット: Livre numérique
言語:Anglais
出版事項: Dordrecht : Springer Netherlands [20..].
Cham : Springer Nature
版:1st ed. 2009.
シリーズ:Lecture Notes in Electrical Engineering 34
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Edition sous un autre format:• Designing Reliable and Efficient Networks on Chips, Texte imprimé, 9781402097560
その他の書誌記述
要約:Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design
記述事項:Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
ISBN:9781402097577
ISSN:1876-1119
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