Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
Guardado en:
| Autor principal: | |
|---|---|
| Formato: | Livre numérique |
| Lenguaje: | Anglais |
| Publicado: |
Dordrecht :
Springer Netherlands
[20..].
Cham : Springer Nature |
| Edición: | 1st ed. 2009. |
| Colección: | Lecture Notes in Electrical Engineering
34 |
| Materias: | |
| Acceso en línea: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Designing Reliable and Efficient Networks on Chips, Texte imprimé, 9781402097560 |
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| 100 | 1 | |a Murali, Srinivasan. | |
| 245 | 1 | 0 | |a Designing Reliable and Efficient Networks on Chips |c by Srinivasan Murali. |
| 250 | |a 1st ed. 2009. | ||
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c [20..]. | ||
| 490 | 0 | |a Lecture Notes in Electrical Engineering |v 34 |x 1876-1119 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 1 | |a NoC Design Methods Designing Crossbar Based Systems Netchip Tool Flow for NoC Design Designing Standard Topologies Designing Custom Topologies Supporting Multiple Applications Supporting Dynamic Application Patterns NoC Reliability Mechanisms Timing-Error Tolerant NoC Design Analysis of NoC Error Recovery Schemes Fault-Tolerant Route Generation NoC Support for Reliable On-Chip Memories Conclusions and Future Directions | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design | ||
| 650 | |a Circuits intégrés | ||
| 650 | |a Systèmes sur puce | ||
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