Static timing analysis for nanometer designs : a practical approach
Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification...
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| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Jezik: | Anglais |
| Izdano: |
Boston, MA :
Springer US
[20..].
Cham : Springer Nature |
| Online dostop: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Sporočilo: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Static Timing Analysis for Nanometer Designs, Texte imprimé, 9780387938196 |
| LEADER | 03273nam a22003137a 4500 | ||
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| 082 | |a 621.3815 | ||
| 100 | 1 | |a Chadha, Rakesh. | |
| 245 | 1 | 0 | |a Static timing analysis for nanometer designs : |b a practical approach |c by Rakesh Chadha, J. Bhasker. |
| 260 | |a Boston, MA : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c [20..]. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 1 | |a STA Concepts Standard Cell Library Interconnect Parasitics Delay Calculation Crosstalk and Noise Configuring the STA Environment Timing Verification Interface Analysis Robust Verification | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers | ||
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| 776 | 0 | |t Static Timing Analysis for Nanometer Designs |b Texte imprimé |z 9780387938196 | |
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| 997 | |0 941456 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||