Low-power high-speed ADCs for nanometer CMOS integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique...
محفوظ في:
| المؤلفون الرئيسيون: | , |
|---|---|
| التنسيق: | Livre numérique |
| اللغة: | Anglais |
| منشور في: |
Dordrecht :
Springer Netherlands
2008.
Cham : Springer Nature |
| سلاسل: | Analog Circuits and Signal Processing
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| الوصول للمادة أونلاين: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| ملاحظة: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9781402084492 • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9789048120031 • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9789048178858 |
جدول المحتويات:
- A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS
- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS
- A 0.4 ps-RMS-Jitter 1 3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification
- Conclusions and Future Directions.