Low-power high-speed ADCs for nanometer CMOS integration
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique...
محفوظ في:
| المؤلفون الرئيسيون: | , |
|---|---|
| التنسيق: | Livre numérique |
| اللغة: | Anglais |
| منشور في: |
Dordrecht :
Springer Netherlands
2008.
Cham : Springer Nature |
| سلاسل: | Analog Circuits and Signal Processing
|
| الوصول للمادة أونلاين: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| ملاحظة: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9781402084492 • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9789048120031 • Low-Power High-Speed ADCs for Nanometer CMOS Integration, Texte imprimé, 9789048178858 |
| LEADER | 03787nam a22003617a 4500 | ||
|---|---|---|---|
| 001 | 940599 | ||
| 008 | 080829s2008 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN127053603 | ||
| 020 | |a 9781402084508 | ||
| 020 | |a 9781402084508 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Cao, Zhiheng. | |
| 245 | 1 | 0 | |a Low-power high-speed ADCs for nanometer CMOS integration |c by Zhiheng Cao, Shouli Yan. |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2008. | ||
| 490 | 0 | |a Analog Circuits and Signal Processing |x 2197-1854 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS -- A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS -- A 0.4 ps-RMS-Jitter 1 3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification -- Conclusions and Future Directions. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. | ||
| 700 | 1 | |a Yan, Shouli. |4 aut | |
| 776 | 0 | |t Low-Power High-Speed ADCs for Nanometer CMOS Integration |b Texte imprimé |z 9781402084492 | |
| 776 | 0 | |t Low-Power High-Speed ADCs for Nanometer CMOS Integration |b Texte imprimé |z 9789048120031 | |
| 776 | 0 | |t Low-Power High-Speed ADCs for Nanometer CMOS Integration |b Texte imprimé |z 9789048178858 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-1-4020-8450-8 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-0PV39D2K-1 |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:74785887X |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/978-1-4020-8450-8 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:750876395 |u https://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/978-1-4020-8450-8 |z Accès INSA CVL | |
| 997 | |0 940599 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||