Low-Power High-Level Synthesis for Nanoscale CMOS Circuits.
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) r...
保存先:
| 主要な著者: | , , , |
|---|---|
| 団体著者: | |
| フォーマット: | Livre numérique |
| 言語: | Anglais |
| 出版事項: |
New York, NY :
Springer US : Imprint: Springer
[20..].
Cham : Springer Nature |
| オンライン･アクセス: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| 注記: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Texte imprimé, 9780387764733 |
目次:
- High-Level Synthesis Fundamentals Power Modeling and Estimation at Transistor and Logic Gate Levels Architectural Power Modeling and Estimation Power Reduction Fundamentals Energy or Average Power Reduction Peak Power Reduction Transient Power Reduction Leakage Power Reduction Conclusions and Future Direction