Low power methodology manual : for system-on-chip design
"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to...
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| 主要な著者: | , , , , |
|---|---|
| フォーマット: | Livre numérique |
| 言語: | Anglais |
| 出版事項: |
New York, NY :
Springer US
2007.
Cham : Springer Nature |
| シリーズ: | Integrated Circuits and Systems
|
| オンライン･アクセス: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| 注記: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low Power Methodology Manual, Texte imprimé, 9781441944184 • Kinematic and dynamic issues in sensor based control, edited by Gaynor E. Taylor, Berlin, Springer-Verlag, 1990, 1 volume (XI-455 p.), NATO ASI series, 0-387-51892-4 • Low power methodology manual, for system-on-chip design, Michael Keating, David Flynn, Robert Aitken... [et al.], [S. l.], Springer, 2007, 1 vol. (XIII-300 p.), 978-0-387-71818-7 |
目次:
- Standard Low Power Methods
- Multi-Voltage Design
- Power Gating Overview
- Designing Power Gating
- Architectural Issues for Power Gating
- A Power Gating Example
- IP Design for Low Power
- Frequency and Voltage Scaling Design
- Examples of Voltage and Frequency Scaling Design
- Implementing Multi-Voltage, Power Gated Designs
- Physical Libraries
- Retention Register Design
- Design of the Power Switching Network.