Routing congestion in VLSI circuits : estimation and optimization
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
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| Główni autorzy: | , , |
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| Format: | Livre numérique |
| Język: | Anglais |
| Wydane: |
New York, NY :
Springer US
2007.
Cham : Springer Nature |
| Seria: | Series on Integrated Circuits and Systems
|
| Dostęp online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Komentarz: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Routing Congestion in VLSI Circuits: Estimation and Optimization, Texte imprimé, 9780387300375 • Routing Congestion in VLSI Circuits, Texte imprimé, 9781441940131 • Gravitational lenses, proceedings of a Conference held at the Massachusetts Institute of Technology, Cambridge, Massachusetts, in honour of Bernard F. Burke's 60th Birthday, June 20, 1988, J. M. Moran, J. N. Hewitt, K. Y. Lo (eds.), Berlin, Springer-Verlag, 1989, 1 vol. (XIV-238 p.), Lecture notes in physics, 3-540-51061-3 |
Spis treści:
- The Origins of Congestion
- An Introduction to Routing Congestion
- The Estimation of Congestion
- Placement-level Metrics for Routing Congestion
- Synthesis-level Metrics for Routing Congestion
- The Optimization of Congestion
- Congestion Optimization During Interconnect Synthesis and Routing
- Congestion Optimization During Placement
- Congestion Optimization During Technology Mapping and Logic Synthesis
- Congestion Implications of High Level Design.