Routing congestion in VLSI circuits : estimation and optimization
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...
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| Hoofdauteurs: | , , |
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| Formaat: | Livre numérique |
| Taal: | Anglais |
| Gepubliceerd in: |
New York, NY :
Springer US
2007.
Cham : Springer Nature |
| Reeks: | Series on Integrated Circuits and Systems
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| Online toegang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Opmerking: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Routing Congestion in VLSI Circuits: Estimation and Optimization, Texte imprimé, 9780387300375 • Routing Congestion in VLSI Circuits, Texte imprimé, 9781441940131 • Gravitational lenses, proceedings of a Conference held at the Massachusetts Institute of Technology, Cambridge, Massachusetts, in honour of Bernard F. Burke's 60th Birthday, June 20, 1988, J. M. Moran, J. N. Hewitt, K. Y. Lo (eds.), Berlin, Springer-Verlag, 1989, 1 vol. (XIV-238 p.), Lecture notes in physics, 3-540-51061-3 |
| Samenvatting: | With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware. Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design. Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers. |
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| Beschrijving item: | Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| ISBN: | 9780387485508 |
| ISSN: | 1558-9420 |
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