Integrated system-level modeling of network-on-chip enabled multi-processor platforms
We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is req...
Tallennettuna:
| Päätekijät: | , , |
|---|---|
| Aineistotyyppi: | Livre numérique |
| Kieli: | Anglais |
| Julkaistu: |
Dordrecht :
Springer Netherlands
[20..].
Cham : Springer Nature |
| Linkit: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Huomautus: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Integrated system-level modeling of network-on-chip enabled multi-processor platforms, Tim Kogel, Rainer Leupers, Heinrich Meyr, Dordrecht, Springer, 2006, 1 vol. (xiv-199 p.), 1-402-04825-4 |
Sisällysluettelo:
- Foreword. Preface 1. Introduction 2. Embedded SOC Applications 3. Classification of Platform Elements 4. System Level Design Principles 5. Related Work 6. Methodology Overview 7. Unified Timing Model 8. MP-SOC Simulation Framework 9. Case Study 10. Summary Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework List of Figures. List of Tables. References Index