Integrated system-level modeling of network-on-chip enabled multi-processor platforms

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is req...

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Auteurs principaux: Kogel, Tim, Leupers, Rainer, 19..- (Auteur), Meyr, Heinrich (Auteur)
פורמט: Livre numérique
שפה:Anglais
יצא לאור: Dordrecht : Springer Netherlands [20..].
Cham : Springer Nature
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Edition sous un autre format:• Integrated system-level modeling of network-on-chip enabled multi-processor platforms, Tim Kogel, Rainer Leupers, Heinrich Meyr, Dordrecht, Springer, 2006, 1 vol. (xiv-199 p.), 1-402-04825-4
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סיכום:We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor
תאור פריט:Archives Springer e-books (Licence nationale)
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ISBN:9781402048265
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